library ieee;
use ieee.std_logic_1164.all;

entity flopr_tb is
end flopr_tb;

architecture behav of flopr_tb is
    component flopr
        generic(n: integer);
        port(
        d : in std_logic_vector(n downto 0);
        clk, rst: in std_logic;
        q : out std_logic_vector(n downto 0)
        );
    end component;

    signal d_s, q_s: std_logic_vector(31 downto 0);
    signal clk_s, rst_s: std_logic;

begin
    FloprTest: flopr
        generic map(31)
        port map(d_s, clk_s, rst_s, q_s);
    process
    begin
        clk_s <= '1';
        wait for 1 ns;
        clk_s <= '0';
        wait for 1 ns;
    end process;

    process
    begin
        rst_s <= '1';
        wait for 1 ns;
        rst_s <= '0';
        d_s <= x"ffffffff"; -- Esto no vale para cualquier n ARREGLAR!
        wait for 1 ns;
        d_s <= x"ffffff00";
        wait for 1 ns;
        d_s <= x"ffff0000";
        rst_s <= '1';
        wait for 1 ns;
    end process;
end behav;
